1. Field
Various embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to an active-precharge operation control of a semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices may store a plurality of data and provide data that is requested. That is, a semiconductor memory device may perform a data write operation for storing data received from an outside of the semiconductor memory device and a data read operation for outputting a data stored in the semiconductor memory device to the outside.
When data is stored in a memory cell of a semiconductor memory device, which is a unit for storing data, particularly, a dynamic random access memory (DRAM), or when data stored in a memory cell of the semiconductor memory device is outputted to the outside, several operations, such as an active operation, a write/read operation, and a precharge operation, have to be performed.
An active operation and a write operation are performed to select a designated memory cell among a plurality of memory cells in a DRAM and to store the data in the selected memory cell. In addition, an active operation and a read operation are performed to select a designated memory cell among a plurality of memory cells in a DRAM and output the data stored in the selected memory cell. A precharge operation is performed to return the DRAM to a state before the active operation is performed.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device.
Referring to FIG. 1, the semiconductor memory device includes a core region 100, an active controller 110, a column controller 120, and an address decoder 160.
The active controller 110 generates a normal active command NM_ACT in response to an external active command EX_ACT and a row address ROW_ADD, and generates a normal precharge command NM_PCG in response to an external precharge command EX_PCG and the row address ROW_ADD.
The column controller 120 generates a normal column command NM_RD/WT in response to an external column command EX_RD/WT and a column address COLUMN_ADD. The external column command EX_RD/WT may be a read command or a write command.
The address decoder 160 generates the row address ROW_ADD and the column address COLUMN_ADD in response to an external address EX_ADD.
The core region 100 is activated in response to the normal active command NM_ACT, precharged in response to the normal precharge command NM_PCG, and performs a column operation of inputting/outputting data in response to the normal column command NM_RD/WT.
As described above, the semiconductor memory device activates the core region 100 in response to the external active command EX_ACT applied from the outside, and precharges the core region 100 in response to the external precharge command EX_PCG applied from the outside. In short, the conventional semiconductor memory device depends on the external commands EX_ACT and EX_PCG inputted from the outside to perform an active-precharge operation.
A section from an application of the external active command EX_ACT to an application of the external precharge command EX_PCG may last longer than a predetermined time (tRASmax), which is set for the semiconductor memory device.
When the core region 100 keeps the active state even after the predetermined time passes, current consumption of the semiconductor memory device may be increased unnecessarily and an erroneous operation may be caused.